Dynamically Reconfigurable Superscalar (DRSS) Processor
Dynamic voltage scaling(DVS) is one of the well-known design techniques
to reduce the power consumption. The key idea is to take into account
the fact that the power consumption is proportional to voltage V squared.
We tried to find another approach.
The key idea for dynamically reconfigurable superscalar (DRSS)
processor is to pay attention to the fact that the cost for the
instruction-issue-logic is proportional to L squared, where L is the
number of the entries of the instruction window. If
- there is no
need for high-performance computation or
- enough parallelism cannot
be found among the instructions in the instruction window,
only the
sub-instruction-issue-logic for a few entries works for the
situation.
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Related publictions
A journal:
- Ryuichi TAKAHASHI and Hajime OHIWA:
"Situated Learning for Fine Grain Microcomputer
Design Education,"(in Japanese)
Journal of JSEE, Vol.54, No.2, pp.55-61 (2006)
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An international conference:
Ryuichi TAKAHASHI and Hajime OHIWA:
"Legitimate Peripheral Participation on FPGA
for Fine-Grain Microprocessor Design Education"...ACM,
IEEE
Proc. 2005 International Conference on
Microelectronic Systems Education, pp.99-100 (2005)
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