 
Profile:
Code name: maruCc04(Nickname:TeI)
Architect: Inoue Tetsuya(Cofabricator:Takahiro Saito)
Became operational:Friday, July 10, 1998
Type: pipelined CISC having 3 stages
Instructions: two-operand format 16bit-instructions x 111
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Special features:
Fully interlocked pipeline
External interruption handling (console)
Internal interruption handling (overflow)
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Machine organization:
Registers: 8bit General purpose registers x 8, 8 bit stack pointer x 0
Logic units: 8 bit ALU x 1, 8 bit barrel shifter x 1
Internal bus: 8 bit x 3(A,B,C)
External bus: 16 bit instruction bus x 1, 8 bit data bus x 1
Main Store: 256Byte x 2 (instruction) + 256Byte (data)
Maximum CPU frequency: 52.632MHz(estimated)
FPGA: Xilinx4010PG191(using 400 CLBs out of 400)
TTL: TI 74 series IC x 26
I/O: 39 switches, 10 LEDs
Application program: Euclidean algorithm, LED control
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Days taken:
System design: 2 weeks (net: 5 days)
CAD: 7 weeks (net: 33 days)
Fabrication: 2 weeks (net: 3 man days)
Debug: 2 weeks (net 10 days)
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A Comment:
I disappointed a little bit since it did not smoke(^^)
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