Profile:

Code name: maruCc05
Architect: Hisashi Iwai (Cofabricator:Kenichi Manabe)
Became operational:Friday, July 17, 1998
Type: pipelined RISC having 3 stages
Instructions: two-operand format 16bit-instructions x 23

Special features:

Special feature is the simplicity in a sense that the machine has no mechanism 
for interruption handling excepting the feature that the pipeline is fully interlocked.

Machine organization:

Registers: 8bit General purpose registers x 3
Logic units: 8 bit ALU x 1
Internal bus: 8 bit x 3
External bus: 16 bit instruction bus x 1, 8 bit data bus x 1
Main Store: 256Byte x 2 (instruction) + 256Byte (data)
Maximum CPU frequency: 40.000MHz
FPGA: Xilinx4010PG191(using 212 CLBs out of 400)
TTL: TI 74 series IC x 26
I/O: 21 switches, 10 LEDs
Application program: Euclidean algorithm

Days taken:

System design: 2 weeks (net: 5 days)
CAD: 5 weeks (net: 20 days)
Fabrication: 2 weeks (net: 7 man days)
Debug: 3 weeks (net 7 days)

Comments:

There was only one wiring mistake, which was very difficult to find.



Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA



Microcomputer Design Educational Environment City-1