Profile:
Code name: maruCc09
Architect: Kouichi Ohta (Cofabricator:Takamori Matsumoto)
Became operational:Monday, Augest 3, 1998
Type: 3 stages-pipelined RISC
Instructions: two-operand format 16bit-instructions x 28
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Special features:
Fully interlocked pipeline
Internal interrupt handling (overflow)
Two's complement arithmetic addition/subtraction
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Machine organization:
Registers: 8bit General purpose registers x 4
Logic units: 8 bit ALU x 1
Internal bus: 8 bit x 3
External bus: 16 bit instruction bus x 1, 8 bit data bus x 1
Main Store: 256Byte x 2 (instruction) + 256Byte (data)
Maximum CPU frequency: 43.5MHz(estimated)
FPGA: Xilinx4010PG191
TTL: TI 74 series IC x 30
I/O: 21 switches, 10 LEDs
Application program: Euclidean algorithm
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Days taken:
System design: 2 weeks (net: 9 days)
CAD: 5 weeks (net: 21 days)
Fabrication: 4 weeks (net: 15 man days)
Debug: 4 weeks (net 18 days)
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