Profile:
Code name: maruCc12 (Nickname:Ca)
Architect: Hiroyasu Obata (Cofabricator:Akio Nakadachi)
Became operational:Friday, July 17, 1998
Type: pipelined RISC having 3 stages
Instructions: two-operand format 16bit-instructions x 18
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Special features:
Fully interlocked pipeline
Internal interruption handling (overflow)
Beautiful wiring that made me possible to find a mistake, which was all, easily
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Machine organization:
Registers: 8bit General purpose registers x 4, 8 bit stack pointer x 1
Logic units: 8 bit ALU x 1
Internal bus: 8 bit x 3
External bus: 16 bit instruction bus x 1, 8 bit data bus x 1
Main Store: 256Byte x 2 (instruction) + 256Byte (data)
Maximum CPU frequency: 43.478MHz(estimated)
FPGA: Xilinx4010PG191(using 306 CLBs out of 400)
TTL: TI 74 series IC x 26
I/O: 21 switches, 10 LEDs
Application program: Euclidean algorithm
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Days taken:
System design: 2 weeks (net: 5 days)
CAD: 5 weeks (net: 20 days)
Fabrication: 2 weeks (net: 6 man days)
Debug: 3 weeks (net 6 days)
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