Profile:

Code name: maruCc13 (Nickname:audly ohzu) Architect: Yoshihiro Kasama (Cofabricator:Shigeyuki Ogi) Became operational:Wednesday, August 5, 1998 Type: 3 stages-pipelined RISC Instructions: two-operand format 16bit-instructions x 15

Special features:

Fully interlocked pipeline Internal interrupt handling (overflow)

Machine organization:

Registers: 8bit General purpose registers x 5 Logic units: 8 bit ALU x 1 Internal bus: 8 bit x 3 External bus: 16 bit instruction bus x 1, 8 bit data bus x 1 Main Store: 256Byte x 2 (instruction) + 256Byte (data) Maximum CPU frequency: 37MHz(estimated) FPGA: Xilinx4010PG191(using 245 CLBs out of 400) TTL: TI 74 series IC x 27 I/O: 28 switches, 18 LEDs Application program: Euclidean algorithm, LED control

Days taken:

System design: 2 weeks (net: 10 days) CAD: 4 weeks (net: 20 days) Fabrication: 7 weeks (net: 30 man days) Debug: 1 weeks (net 7 days)

Comments:

I was rather surprised to find it works.

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Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA

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Microcomputer Design Educational Environment City-1

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