Product introduction



Great line-up

CELICA/ALPHONCE, The maruCc06/maruCc14 series of the ability.
Chose maruCcTM06/14 series with the 3rd generation CPUs.


8 registers can carry out almost all of the computations with no data-memory access,
which enables us to enjoy 50% (our company ratio) speed up...liar!

We offer you super excellent line-ups of maruCc14 and maruCc06. The latter is good at
branch instructions and the former is the fastest among all maruCc series computers...liar!

Approved CPU performance of our machines has been widely extended to fit for your needs to
develop strategic machines to compete with the other highly motivated machines...too big talker!
Specifications list
Development code maruCc14
Instruction head 2byte
Instruction set RISC
Instruction form 1 address load-store
FPGA Xilinx 4010pg191
Number of registers 8bit general-purpose register x8
ALU 8bit
Internal Bus 8bit 3 system
External Bus 16bit Instruction bus 8bit data bus
Main memory 256x2 byte Instruction memory
256byte data memory
Characteristics Interruption function from the outside is carried. (It is operated by hand from console.)
perfect interlock mechanism is carried.
I/O switchx22. LEDx10. 7segment-ledx1
aplication Euclidean algorithm, Knight rider
Maximum CPU frequency32MHz
Number of TTL 30(74series)



Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA


Microcomputer Design Educational Environment City-1