 
Profile:
Code name: maruCc17
Architect: Takahiro Saito (Cofabricator:Tetuya Inoue)
Became operational:Friday, July 17, 1998
Type: pipelined CISC having 3 stages
Instructions: zero-operand format 8bit-instructions x 32
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Special features:
Fully interlocked pipeline
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Machine organization:
Registers: 8bit General purpose registers x 8
Logic units: 8 bit ALU x 1
Internal bus: 8 bit x 3
External bus: 8 bit instruction bus x 1, 8 bit data bus x 1
Main Store: 256Byte (instruction) + 256Byte (data)
Maximum CPU frequency: 62.5MHz(estimated)
FPGA: Xilinx4010PG191(using 381 CLBs out of 400)
TTL: TI 74 series IC x 26
I/O: 32 switches, 10 LEDs
Application program: Euclidean algorithm
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Days taken:
System design: 2 weeks (net: 5 days)
CAD: 5 weeks (net: 20 days)
Fabrication: 2 weeks (net: 6 man days)
Debug: 2 weeks (net 7 days)
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