| Profile |
|---|
| Code name | maruCc21 (Nickname:ZEPHYRANTHES) |
| Architect | Yasunobu Sanada (Cofabricator:Kentaro Higashi) |
| Became operational | Friday, July 17, 1998 |
| Type | pipelined RISC having 3 stages |
| Instructions | two-operand format 16bit-instructions x 25 |
| Special features |
|---|
| Fully interlocked pipeline |
| Internal interrupt handling (overflow) |
| Indication by 7-segment LED(need anather FPGA) |
| Change of the clock frequency(0.008Hz - 1MHz) |
| Negative number expression by the two's complement |
| Machine organization |
|---|
| Registers | 8bit General purpose registers x 4 |
| Logic units | 8 bit ALU x 1 |
| Internal bus | 8 bit x 3 |
| External bus | 16 bit instruction bus x 1, 8 bit data bus x 1 |
| Main Store | 256Byte x 2 (instruction) + 256Byte (data) |
| CPU frequency |
| (cost priority) 41.667MHz |
| (speed priority)71.429MHz |
| FPGA | Xilinx4010PG191(using 304 CLBs out of 400) |
| TTL | TI 74 series IC x 29 |
| I/O | switch x 21, LED x 10, 7segment LED x 1 |
| Application program | Euclidean algorithm, etc
It can be made by the special assembler. |
| Days taken |
|---|
| System design | 2 weeks (net: 10 days) |
| CAD | 6 weeks (net: 30 days) |
| Fabrication | 4 weeks (net: 40 man days) |
| Debug | 5 weeks (net 25 days) |
| Comments |
|---|
| We made many mistakes, which made the debugging difficult, but I love my machine all the more. |
