Profile:

Code name: maruCc24 Architect: Yoshinori Takeoka (Cofabricator:Yuu Eshima) Became operational:Friday, July 24, 1998 Type: pipelined RISC having 3 stages Instructions: two-operand format 16bit-instructions x 7

Special features:

Fully interlocked pipeline Internal interruption handling (overflow) Two's complement arithmetic addition/subtraction Wiring is stick out of the board

Machine organization:

Registers: 8bit General purpose registers x 4 Logic units: 8 bit ALU x 1 Internal bus: 8 bit x 3 External bus: 16 bit instruction bus x 1, 8 bit data bus x 1 Main Store: 256Byte x 2 (instruction) + 256Byte (data) Maximum CPU frequency: 45.455MHz FPGA: Xilinx4010PG191(using 182 CLBs out of 400) TTL: TI 74 series IC x 26 I/O: 21 switches, 10 LEDs Application program: Euclidean algorithm

Days taken:

System design: 2 weeks (net: 5 days) CAD: 5 weeks (net: 20 days) Fabrication: 3 weeks (net: 7 days) Debug: 3 weeks (net 5 days)

Comments:

Ifve learned many things through this course.

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Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA

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Microcomputer Design Educational Environment City-1

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