 
Profile:
Code name: maruCc25 (Nickname:manbou)
Architect: Miki Tanaka(Cofabricator:Waki Murakami)
Became operational:Friday, July 31, 1998
Type: pipelined RISC having 3 stages
Instructions: two-operand format 16bit-instructions x 10
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Special features:
Fully interlocked pipeline
Overflow indicator
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Machine organization:
Registers: 8bit General purpose registers x 4
Logic units: 8 bit ALU x 1
Internal bus: 8 bit x 3
External bus: 16 bit instruction bus x 1, 8 bit data bus x 1
Main Store: 256Byte x 2 (instruction) + 256Byte (data)
Maximum CPU frequency: 62.5MHz
FPGA: Xilinx4010PG191(using 256 CLBs out of 400)
TTL: TI 74 series IC x 28
I/O: 22 switches, 12 LEDs
Application program: Euclidean algorithm
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Days taken:
System design: about 3 weeks
CAD: about 5 weeks
Fabrication: about 2 weeks
Debug: about 2 weeks
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