Profile:
Code name: maruCc29 (Nickname:CLAVIA 2.0GT)
Architect: Daisuke Hamasaki (Cofabricator:Shinya Hiraike)
Became operational:Monday, August 10, 1998
Type: pipelined RISC having 3 stages
Instructions: two-operand format 16bit-instructions x 32
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Special features:
Fully interlocked pipeline
Internal interruption handling (overflow)
Instruction sets includes those for Multiplication and Division
7 segments LED x 2
Dip-switch for operating clock
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Machine organization:
Registers: 8bit General purpose registers x 5 (including Accumulator)
Logic units: 8 bit ALU x 1
Internal bus: 12 bit x 1, 8 bit x 2
External bus: 16 bit instruction bus x 1, 12 bit data bus x 1
Main Store: 256Byte x 2 (instruction) + 4096Byte (data)
Maximum CPU frequency: 33MHz(estimated)
FPGA: Xilinx4010PG191(using 400 CLBs out of 400)
TTL: TI 74 series IC x 36
I/O: 25 switches, 2 LEDs, 2 seven segments LEDs
Application program: Euclidean algorithm
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Days taken:
System design: 2 weeks (net: 5 days)
CAD: 5 weeks (net: 20 days)
Fabrication: 2 weeks (net: 8 man days)
Debug: 2 weeks more (net 10 days)
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