| Profile |
|---|
| Code name | maruCc31 (Nickname:Doranikov) |
| Architect | Kentaro Higashi (Cofabricator:Yasunobu Sanada) |
| Became operational | Friday, July 17, 1998 |
| Type | pipelined RISC having 3 stages |
| Instructions | two-operand format 16bit-instructions x 23 |
| Special features |
|---|
| Fully interlocked pipeline |
| Indication by 7-segment LED |
| Overflow detection |
| Change of the clock frequency(0.008Hz〜1MHz) |
| Negative number expression by the two's complement |
| Machine organization |
|---|
| Registers | 8bit General purpose registers x 5 |
| Logic units | 8 bit ALU x 1 |
| Internal bus | 8 bit x 3 |
| External bus | 16 bit instruction bus x 1, 8 bit data bus x 1 |
| Main Store | 256Byte x 2 (instruction) + 256Byte (data) |
| Maximum CPU frequency | 35.714MHz(estimated) |
| FPGA | Xilinx4010PG191(using 318 CLBs out of 400) |
| TTL | TI 74 series IC x 29 |
| I/O | 21 switches, 10 LEDs |
| Application program | Euclidean algorithm |
| Days taken |
|---|
| System design | 2 weeks (net: 10 days) |
| CAD | 6 weeks (net: 30 days) |
| Fabrication | 4 weeks (net: 40 man days) |
| Debug | 5 weeks (net 25 days) |
| Comments |
|---|
| I was glad watching my machine working all the more because I had big difficulties in designing and assembling. This course was a very good experience for me. |
