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Computer created by me at the first time in my life.
Code name: maruCc33 (Nickname:Kuriddokun) |
Special features:
Fully interlocked pipeline
External interruption handling (console)
Internal interruption handling (overflow)
Machine organization:
Registers: 8bit General purpose registers x 4
Logic units: 8 bit ALU x 1
Internal bus: 8 bit x 3
External bus: 16 bit instruction bus x 1, 8 bit data bus x 1
Main Store: 256Byte x 2 (instruction) + 256Byte (data)
Maximum CPU frequency: 44MHz(estimated)
FPGA: Xilinx4010PG191(using 256 CLBs out of 400)
TTL: TI 74 series IC x 26
I/O: 22 switches, 10 LEDs
Application program: Euclidean algorithm, LED control
Days taken:
System design: 2 weeks (net: 5 days)
CAD: 5 weeks (net: 20 days)
Fabrication: 2 weeks (net: 6 man days)
Debug: 2 weeks (net 4 days)
Comments:
It was hard to find where we should start the debugging.
Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA
Microcomputer Design Educational Environment City-1
Fully interlocked pipeline |
Registers: 8bit General purpose registers x 4 |
Days taken:
System design: 2 weeks (net: 5 days)
CAD: 5 weeks (net: 20 days)
Fabrication: 2 weeks (net: 6 man days)
Debug: 2 weeks (net 4 days)
Comments:
It was hard to find where we should start the debugging.
Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA
Microcomputer Design Educational Environment City-1
System design: 2 weeks (net: 5 days) |
It was hard to find where we should start the debugging. |