Profile
Code name : maruCc36
Architect : Takamori Matsumoto(Cofabricator : Kouichi Oota)
Became operational : Monday, August, 3, 1998
Type : pipelined RISC having 3 stages
Instructions : two-operand format 16bit-instructions x 23
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Special features
Fully interlocked pipeline
Two's complement arithmetic addition/subtraction
Internal interruption handling (overflow)
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Machine organization
Registers : 8bit General purpose registers x 5
Logic units : 8 bit ALU x 1
Internal bus : 8 bit x 3
External bus : 16 bit instruction bus x 1, 8 bit data bus x 1
Main Store : 256Byte x 2 (instruction) + 256Byte (data)
Maximum CPU frequency : 35.714MHz(estimated)
FPGA : Xilinx4010PG191
TTL : TI 74 series IC x 30
I/O : 21 switches, 10 LEDs
Application program : Euclidean algorithm
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