Profile:

Code name: maruCc40 Architect: Kenichi Manabe (Cofabricator:Hisashi Iwai) Became operational:Friday, July 17, 1998 Type: pipelined RISC having 3 stages Instructions: two-operand format 16bit-instructions x 19

Special features:

There is no special feature on this machine since I concentrated all my effort to make it work. I donft care for this at all since it worked!

Machine organization:

Registers: 8bit General purpose registers x 3 Logic units: 8 bit ALU x 1 Internal bus: 8 bit x 3 External bus: 16 bit instruction bus x 1, 8 bit data bus x 1 Main Store: 256Byte x 2 (instruction) + 256Byte (data) Maximum CPU frequency: 47.619MHz FPGA: Xilinx4010PG191(using 197 CLBs out of 400) TTL: TI 74 series IC x 26 I/O: 21 switches, 10 LEDs Application program: Euclidean algorithm

Days taken:

System design: 2 weeks (net: 5 days) CAD: 5 weeks (net: 20 days) Fabrication: 2 weeks (net: 7 man days) Debug: 3 weeks (net 7 days)

Comments:

I irritated so much with unordinary behavior of this machine until the final moment when it worked as I expected.

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Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA

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Microcomputer Design Educational Environment City-1

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