Profile:

Code name: maruCc46 (Nickname:maru-C) Architect: Atsushi Mori (Cofabricator:Kenji Sakaguchi) Became operational:Monday, August 3, 1998 Type: pipelined RISC having 3 stages Instructions: two-operand format 16bit-instructions x 16

Special features:

Fully interlocked pipeline Pretty labels on the machine for the guidance

Machine organization:

Registers: 8bit General purpose registers x 6, 2 bit flag register x 1 Logic units: 8 bit ALU x 1 Internal bus: 8 bit x 3 External bus: 16 bit instruction bus x 1, 8 bit data bus x 1 Main Store: 256Byte x 2 (instruction) + 256Byte (data) Maximum CPU frequency: 40.0MHz(estimated) FPGA: Xilinx4010PG191(using 256 CLBs out of 400) TTL: TI 74 series IC x 29 I/O: 21 switches, 10 LEDs Application program: Euclidean algorithm

Days taken:

System design: 2 weeks (net: 5 days) CAD: 10 weeks (net: 20 days) Fabrication: 2 weeks (net: 6 man days) Debug: 1 weeks (net 2 days)

Comments:

I almost gave up but I accomplished. I was glad when I completed.

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Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA

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Microcomputer Design Educational Environment City-1

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