Profile:

Code name: maruCc51 (Nickname:Mad Pumpkin) Architect: Tetsuo YOSHIDA (Cofabricator:Susumu KODAKARI) Became operational:Friday, July 17, 1998 Type: pipelined RISC having 3 stages Instructions: two-operand format 16bit-instructions x 13

Special features:

Incompletely interlocked pipeline Negative number expression by the two's complement

Machine organization:

Registers: 8bit General purpose registers x 3 Logic units: 8 bit ALU x 1 Internal bus: 8 bit x 3 External bus: 16 bit instruction bus x 1, 8 bit data bus x 1 Main Store: 256Byte x 2 (instruction) + 256Byte (data) Maximum CPU frequency: 43.478MHz(estimated) FPGA: Xilinx4010PG191(using 256 CLBs out of 400) TTL: TI 74 series IC x 28 I/O: 22 switches, 10 LEDs Application program: Euclidean algorithm

Days taken:

System design: 2 weeks (net: 10 days) CAD: 6 weeks (net: 30 days) Fabrication: 2 weeks (net: 10 days) Debug: 3 weeks (net 20 days)

Comments:

I've got tired.

---

Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA

---

Microcomputer Design Educational Environment City-1

---