Profile:

Code name: maruCc53 (Nickname:Maru-chyan) Architect: Masahiro Kitanaka (Cofabricator:Masayuki Hiragori) Became operational:Wednesday, August 5, 1998 Type: pipelined CISC having 3 stages Instructions: two-operand format 16bit-instructions x 14

Special features:

Fully interlocked pipeline Internal interruption handling (overflow)

Machine organization:

Registers: 8bit General purpose registers x 8 Logic units: 8 bit ALU x 1 Internal bus: 8 bit x 3 External bus: 16 bit instruction bus x 1, 8 bit data bus x 1 Main Store: 256Byte x 2 (instruction) + 256Byte (data) Maximum CPU frequency: 50MHz(estimated) FPGA: Xilinx4010PG191(using 256 CLBs out of 400) TTL: TI 74 series IC x 31 I/O: 22 switches, 10 LEDs Application program: Euclidean algorithm, LED control

Days taken:

System design: 1 weeks (net: 5 days) CAD: 6 weeks (net: 20 days) Fabrication: 2 weeks (net: 6 days) Debug: 1 weeks (net 4 days)

Comments:

I was almost given up until I could find a wiring mistake. I satisfied when it worked.

---

Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA

---

Microcomputer Design Educational Environment City-1

---