maruCc56
Profile:
Code name: maruCc56 (Nickname:Espresso)
Architect: Masayuki HIRAGOURI (Cofabricator:Masahiro KITANAKA)
Became operational:Wednesday, August 5, 1998
Type: pipelined CISC having 3 stages
Instructions: two-operand format 16bit-instructions x 12
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Special features:
Fully interlocked pipeline
Internal interruption handling (overflow)
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Machine organization:
Registers: 8bit General purpose registers x 3, 8 bit stack pointer x 1
Logic units: 8 bit ALU x 1
Internal bus: 8 bit x 3
External bus: 16 bit instruction bus x 1, 8 bit data bus x 1
Main Store: 256Byte x 2 (instruction) + 256Byte (data)
Maximum CPU frequency: 44MHz(estimated)
FPGA: Xilinx4010PG191(using 256 CLBs out of 400)
TTL: TI 74 series IC x 33
I/O: 22 switches, 10 LEDs
Application program: Euclidean algorithm
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Days taken:
System design: 2 weeks (net: 5 days)
CAD: 5 weeks (net: 20 days)
Fabrication: 3 weeks (net: 11 days)
Debug: 3 weeks (net 16 days)
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Comments:
Special thanks to my partner Masahiro KITANAKA.
Without him, the machine might fail to be completed.
Although there were few troubles in the software for the machine,
there were many mistakes in soldering and wirings.
I named my machine "Espresso" wishing the fast completion.
I felt sorrow to find the slow progress.
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