Microcomputer Design Educational Environment City-1 on Verilog HDL and FPGA in 1996
for the junior students of the Department of Computer Engineering,
Faculty of Information Sciences, Hiroshima City University
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A video City-1 is introducing the first 3 years (1996-1998) of City-1, which is an educational course held successfully by Ryuichi TAKAHASHI in microcomputer design using field programmable gate arrays (FPGAs) for the junior students of the Department of Computer Engineering, Faculty of Information Sciences, Hiroshima City University until 2008.
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50 students, out of 53 students, succeeded to complete all phases in 1996. About half of them succeeded to
make their machines execute "Quicksort" given as the
specification that should run on their machines.
3 of the students succeeded to complete
pipelined RISC having from 2 to 4 stages. One of the pipelined RISC
named maruCa58, designed by a female student (right picture) instructed carefully by me (Ryuichi TAKAHASHI), was fully interlocked. This machine was the fastest for
the application program Quicksort given as the specification for the
machine.
The following figure illustrates "Prefetch Unit" described by the female student, who named the unit "cuf." The logic synthesizer in those days could handle "assign" and "deassign" for the registers in Verilog HDL:
Figure 1. A state machine description for maruCa58
The following figure illustrates the block diagram drawn by her:
Figure 2. The block diagram for the maruCa58
An incompletely specified CISC RTL description, named
CISC-1, which I wrote in 573 lines for 7 modules in Verilog HDL,
was given to all other students as an example description.
This example description CISC-1 was unique in a point that it uses a
horizontal microcode like state assignment for the control unit to implement the CISC machine, which we call hardwired microcode machine.
Ryuichi TAKAHASHI
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