Microcomputer Design Educational Environment City-1 on Verilog HDL and FPGA in 1997
for the junior students of the Department of Computer Engineering,
Faculty of Information Sciences, Hiroshima City University
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A video City-1 is introducing the first 3 years (1996-1998) of City-1, which is an educational course held successfully by Ryuichi TAKAHASHI in microcomputer design using field programmable gate arrays (FPGAs) for the junior students of the Department of Computer Engineering, Faculty of Information Sciences, Hiroshima City University until 2008.
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Ryuichi TAKAHASHI wrote down a pipelined CISC, having 3 stages, behavioral description, named CISC-3 with 16 bits instruction-bus and 8 bits data-bus, to present to all of the 54 junior students in the spring of 1997.
CISC-3 was written in 639 lines for 9 modules in Verilog HDL.
As a result, 47 students, out of 54 students, succeeded to complete very sound pipelining.
28 students completed pipelined RISC and 19 students completed pipelined CISC this year.
All of the machines were fully interlocked. All of the machines achieved the sound throughput: 1 clock cycle per instruction (CPI).
The number of the instructions was from 23 to 85. The number of
the registers was from 4 to 16. A pipelined CISC had 24 bits (3 Byte)
for the instructions.
The quantitative approach is important especially for commercially
successful architecture design. However, we thought fully interlocked
pipelining could be more educationally effective for the junior
students to understand the role of data-dependencies among
instructions.
Ryuichi TAKAHASHI
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