Profile
Code name	maruCc16 (Nickname:Limit-I)
Architect	Susumu Kodakari (Cofabricator:Tetsuo Yoshida)
Became operational	Friday, July 17, 1998
Type	pipelined RISC having 3 stages
Instructions	two-operand format 16bit-instructions x 18

Special features
Fully interlocked pipeline
Internal interrupt handling (overflow)
Negative number expression by the two's complement

Machine organization
Registers	8bit General purpose registers x 4
Logic units	8 bit ALU x 1
Internal bus	8 bit x 3
External bus	16 bit instruction bus x 1 8 bit data bus x 1
Main Store	256Byte x 2 (instruction) 256Byte (data)
Maximum CPU frequency	43.478MHz(estimated)
FPGA	Xilinx4010PG191 (using 258 CLBs out of 400)
TTL	TI 74 series IC x 28
I/O	22 switches, 10 LEDs
Application program	Euclidean algorithm

Days taken
System design	2 weeks (net: 10 days)
CAD	6 weeks (net: 30 days)
Fabrication	2 weeks (net: 10 days)
Debug	4 weeks (net 20 days)

Comments
It was hard to fix the problem of data memory access timing caused by the modification into a single phase clocking scheme. It was a good experience for me to learn the Verilog HDL.