Profile:

Code name: maruCc49 (Nickname:Isana.mx1 [Isana mean whale in japan])
Architect: Yuki Yamaguchi (Cofabricator:Hideaki Mukai)
Became operational:Friday, July 10, 1998
Type: pipelined RISC having 3 stages
Instructions: two-operand format 16bit-instructions x 20

Special features:

Fully interlocked pipeline
External interruption handling (console)
Internal interruption handling (overflow)
Negative numbers expression by the two's complement
Perfect single phase clocking scheme

Machine organization:

Registers: 8bit General purpose registers x 4, A speciall registers x 1(For jump)
Logic units: 8 bit ALU x 1
Internal bus: 8 bit x 3
External bus: 16 bit instruction bus x 1, 8 bit data bus x 1
Main Store: 256Byte x 2 (instruction) + 256Byte (data)
Maximum CPU frequency: 44MHz(estimated)
FPGA: Xilinx4010PG191(using 265 CLBs out of 400)
TTL: TI 74 series IC x 28
I/O: 22 switches, 13 LEDs
Application programs: Euclidean algorithm, LED control

Days taken:

System design: 2 weeks (net: 5 days)
CAD: 5 weeks (net: 20 days)
Fabrication: 2 weeks (net: 6 man days)
Debug: 4 weeks (net 14 days)

Comments:

I was very happy to be able to implement external interruption handling above all.



A Computer created by me for the first time in my life. (in Japanese)



Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA



Microcomputer Design Educational Environment City-1