Special features
Fully interlocked pipeline Internal interruption handling (overflow)

Machine organization
Registers	8bit General purpose registers x 6
Logic units	8 bit ALU x 1
Internal bus	8 bit x 3
External bus	16 bit instruction bus x 1 8 bit data bus x 1
Main Store	256Byte x 2 (instruction) 256Byte (data)
Maximum CPU frequency	40MHz(estimated)
FPGA	Xilinx4010PG191 (using 256 CLBs out of 400)
TTL	TI 74 series IC x 25
I/O	22 switches, 10 LEDs
Application program	Euclidean algorithm

Days taken
System design	2 weeks (net: 5 days)
CAD	5 weeks (net: 20 days)
Fabrication	2 weeks (net: 6 man days)
Debug	4 weeks (net 20 days)

Comments
It was hard to synchronizing all of the register transfer operations with a single clock pulse. Above all, it took long time for debugging the error on the data memory access control. I spent tough days but I was glad when my machine worked all the more.

Computer Engineering Experiment City-1 in 1998 on Verilog HDL and FPGA

Microcomputer Design Educational Environment City-1

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