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A special method for City-1
when you broke your FPGA
"Rehkopf's Method" is a special way to continue the entire design and fabrication
phases even in the case when you broke the FPGA soldered together
with the printed circuit board.
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"Rehkopf's Method" was developed by a German student who joined City-1 in 2004 and named after the name of this student: Maximilian REHKOPF. He broke the FPGA during his debugging effort for the FPGA board supplying the electricity...He looked so sad with the broken board. I was depressed so much looking at him who joined my class from a far country. In the next day, he visited my office with a smile to report that he found a very unique way to fix it.
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This method was used again in 2006:
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3 students in the left picture worked faster than the others until they broke the FPGA.
The German student Rehkopf was one of the first students who used the 200,000 gates FPGA. He asked me for another FPGA board in the day after the day when he broke the FPGA. I gave it since it was a trial and he was from a far country. Although I felt relief at his success, I thought this method is not for the other students in the future since it was too expensive to use another new FPGA board with special pins for the connection.
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I talked about this German student and said "another new board is too expensive" to the 3 students.
There were used FPGA boards in the recycling phase (left picture) in a room next to the laboratory for City-1. The 3 students wished to use the used FPGA board. Reusing the used FPGA with pins seemed to be welcome.
I said GO.
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In the first step of "Rehkopf's method," broken FPGA is removed. Left picture illustrates the board after this step.
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Then, used FPGA with pins is removed. Left picture illustrates this step.
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The pins for the used FPGA are set on the pins for the broken FPGA.
It was a very exciting moment when 3 students succeeded to configure their designs.
They succeeded to run the Euclidean algorithm.
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Click here for the page by the German student Maximilian REHKOPF.
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The orthodox method is to use prior 10,000 gates FPGA when you broke the 200,000 gates FPGA. One could learn more when the one failed.
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