|
maruCc(TM) Series
the sixth.
bdkhb` AppearanceII
 |
For the first time, Dual FPGA loading. |
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The rich divergence order of answering every request
of the user's. |
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The outside profit gets crowded, function loading. |
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The interface which is easy to understand by 7 segment
LED. |
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Knight Rider order, standard equipment. |
Machine organization yCELICAz
| Type |
pipelined RISC having 3 stages |
| Instructions |
two-operand format 16bit-instructions |
| Registers |
8bit General purpose registers x 4 |
| Logic units |
8 bit ALU x 1 |
| Internal bus |
8 bit x 3 |
| External bus |
16 bit instruction bus x 1, 8 bit data bus x 1 |
| Main Store |
256Byte x 2 (instruction) + 256Byte (data) |
| Maximum CPU frequency |
28.571lgiestimatedj |
| eof` |
Xilinx 4010PG191 iusing 241 CLBs out of 400j
Xilinx 4010PG191 iusing 15 CLBs out of 400j |
| TTL |
TI 74 series IC x 29 |
| I/O |
22 switches, 10LEDs, 1 7 segment LED |
| Application program |
Euclidean algorithm, LED control |
Order list
| Sketch issue |
The address mode |
Order function |
| HLT |
00 |
00 |
HaLT |
| LD |
{reg} |
{mem} |
LoaD |
| ST |
{reg} |
{mem} |
STore |
| CPY |
{reg} |
{reg} |
CoPY |
| ADD |
{reg} |
{reg} |
ADD |
| ADI |
{reg} |
{imm} |
ADd Immediate |
| SUB |
{reg} |
{reg} |
SUBtract |
| SBI |
{reg} |
{imm} |
SuBtract Immediate |
| CMP |
{reg} |
{reg} |
CoMPare |
| CPI |
{reg} |
{imm} |
ComPare Immediate |
| SLL |
{reg} |
00 |
Shift Left Logically |
| SRL |
{reg} |
00 |
Shift Right Logically |
| BA |
00 |
{imm} |
Branch Always |
| BV |
00 |
{imm} |
Branch on oVerflow |
| BZ |
00 |
{imm} |
Branch on Zero |
| BNZ |
00 |
{imm} |
Branch on Not Zero |
| BN |
00 |
{imm} |
Branch on Negative |
| BZP |
00 |
{imm} |
Branch on Zero or Positive |
| BP |
00 |
{imm} |
Branch on Positive |
| BZN |
00 |
{imm} |
Branch on Zero or Negative |
| BC |
00 |
{imm} |
Branch on Carry |
| BNC |
00 |
{imm} |
Branch on Not Carry |
| BGE |
00 |
{imm} |
Branch on Greater than or Equal |
| BGT |
00 |
{imm} |
Branch on Greater Than |
| BLE |
00 |
{imm} |
Branch on Less than or Equal |
| BLT |
00 |
{imm} |
Branch on Less Than |
Days taken
| System design |
: |
2weeks |
|
| CAD |
: |
7weeks |
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| Fabrication |
: |
3weeks |
|
| Debug |
: |
4weeks |
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| Became operationa |
: |
July 3, 1998 (Board)
August 4, 1998 (CPU) |
Cements
It was easy as pie until checking the DMA. After that, I wasted a terrific time.
The subjects of this course can be regarded as settled, since the
Euclidean algorithm appeared to be easy to clear.
It was not true for my original functions planned.
It will be a good funny story when this past is looked back.
The summer vacation has been already started when I was convinced of the efforts.
I am not good at speaking English. So please look at Japanese
page for a delicate shade of meaning.
Architect: Tomohiro Ueno (Cofabricator:Yoichi Kawano)
Alphonce's
Home Page
Microcomputer Design Educational Environment City-1
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